本工程板级支持包文件适用于野火stm32f429 开发板。
bsp_clk.c
/**
******************************************************************************
* @file bsp_clk.c
* @author Waao
* @version V1.0.0
* @date 21-Dec-2018
* @brief This file contains some board support package\'s functions for the CLK.
*
******************************************************************************
* @attention
*
* None
*
******************************************************************************
*/
#include <bsp_clk.h>
/**
* @brief Initialize the SYSCLK powered by HSE
* @note None
* @param m: VOC input clock\'s frequency division factor.
* n: VOC output clock\'s frequency doubling factor.
* p: PLLCLK clock\'s frequency division factor.
* q: OTG, FS, SDIO and RNG clock\'s frequency division factor.
* @retval None
*/
void HSE_SetSysClock(uint32_t m, uint32_t n, uint32_t p, uint32_t q)
{
__IO uint32_t HSEStartUpStatus = 0;
//Enable the HSE, open the external crystal oscillator
RCC_HSEConfig(RCC_HSE_ON);
//Waiting the HSE to be stable
HSEStartUpStatus = RCC_WaitForHSEStartUp();
if(HSEStartUpStatus == SUCCESS)
{
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
//HCLK = SYSCLK / 1
RCC_HCLKConfig(RCC_SYSCLK_Div1);
//PCLK2 = HCLK / 2
RCC_PCLK2Config(RCC_HCLK_Div2);
//PCLK1 = HCLK / 4
RCC_PCLK1Config(RCC_HCLK_Div4);
//Configure the PLL
RCC_PLLConfig(RCC_PLLSource_HSE, m, n, p, q);
//Enable the PLL
RCC_PLLCmd(ENABLE);
//Waiting the PLL to be stable
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/*--------------------------------------------*/
//Open the OVER-RIDE mode to reach a higher frequency
PWR->CR |= PWR_CR_ODEN;
while((PWR->CSR & PWR_CSR_ODRDY) == 0)
{
}
PWR->CR |= PWR_CR_ODSWEN;
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
{
}
//Configure the FLASH
FLASH->ACR = FLASH_ACR_PRFTEN
|FLASH_ACR_ICEN
|FLASH_ACR_DCEN
|FLASH_ACR_LATENCY_5WS;
/*---------------------------------------------*/
//Change the clock of the PLL to SYSCLK when PLL to be stable
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
else
{
while(1)
{
}
}
}
/**
* @brief Initialize the SYSCLK powered by HSI
* @note None
* @param m: VOC input clock\'s frequency division factor.
* n: VOC output clock\'s frequency doubling factor.
* p: PLLCLK clock\'s frequency division factor.
* q: OTG, FS, SDIO and RNG clock\'s frequency division factor.
* @retval None
*/
void HSI_SetSysClock(uint32_t m, uint32_t n, uint32_t p, uint32_t q)
{
__IO uint32_t HSIStartUpStatus = 0;
//Initialize the RCC parameter to reset status
RCC_DeInit();
//Enable the HSI, HSI=16M
RCC_HSICmd(ENABLE);
//Waiting the HSI to be ready
HSIStartUpStatus = RCC->CR & RCC_CR_HSIRDY;
//Continue to run only when the HSI to be ready
if(HSIStartUpStatus == RCC_CR_HSIRDY)
{
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
PWR->CR |= PWR_CR_VOS;
//HCLK = SYSCLK / 1
RCC_HCLKConfig(RCC_SYSCLK_Div1);
//PCLK2 = HCLK / 2
RCC_PCLK2Config(RCC_HCLK_Div2);
//PCLK1 = HCLK / 4
RCC_PCLK1Config(RCC_HCLK_Div4);
//Configure the PLL
RCC_PLLConfig(RCC_PLLSource_HSI, m, n, p, q);
//Enable the PLL
RCC_PLLCmd(ENABLE);
//Waiting the PLL to be stable
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/*--------------------------------------------*/
//Open the OVER-RIDE mode to reach a higher frequency
PWR->CR |= PWR_CR_ODEN;
while((PWR->CSR & PWR_CSR_ODRDY) == 0)
{
}
PWR->CR |= PWR_CR_ODSWEN;
while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
{
}
//Configure the FLASH
FLASH->ACR = FLASH_ACR_PRFTEN
|FLASH_ACR_ICEN
|FLASH_ACR_DCEN
|FLASH_ACR_LATENCY_5WS;
/*---------------------------------------------*/
//Change the clock of the PLL to SYSCLK when PLL to be stable
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
while(RCC_GetSYSCLKSource() != 0x08)
{
}
}
else
{
while(1)
{
}
}
}
/**
* @brief Configure the MCO1 output the clock signal
* @note None
* @param None
* @retval None
*/
void MCO1_GPIO_Config(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(MCO1_CLK_PORT, ENABLE);
GPIO_InitStructure.GPIO_Pin = MCO1_PIN;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(MCO1_PORT, &GPIO_InitStructure);
}
/**
* @brief Configure the MCO2 output the clock signal
* @note None
* @param None
* @retval None
*/
void MCO2_GPIO_Config(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_AHB1PeriphClockCmd(MCO2_CLK_PORT, ENABLE);
GPIO_InitStructure.GPIO_Pin = MCO2_PIN;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(MCO2_PORT, &GPIO_InitStructure);
}
bsp_clk.h
/**
******************************************************************************
* @file bsp_clk.h
* @author Waao
* @version V1.0.0
* @date 21-Dec-2018
* @brief This file contains some board support package\'s definition for the CLK.
*
******************************************************************************
* @attention
*
* None
*
******************************************************************************
*/
#ifndef __BSP_LED_H_
#define __BSP_LED_H_
#include <stm32f4xx.h>
#define PLL_M 25
#define PLL_N 360
#define PLL_P 2
#define PLL_Q 7
#define MCO1_PIN GPIO_Pin_8
#define MCO1_PORT GPIOA
#define MCO1_CLK_PORT RCC_AHB1Periph_GPIOA
#define MCO2_PIN GPIO_Pin_9
#define MCO2_PORT GPIOC
#define MCO2_CLK_PORT RCC_AHB1Periph_GPIOC
void HSE_SetSysClock(uint32_t m, uint32_t n, uint32_t p, uint32_t q);
void HSI_SetSysClock(uint32_t m, uint32_t n, uint32_t p, uint32_t q);
void MCO1_GPIO_Config(void);
void MCO2_GPIO_Config(void);
#endif
继续阅读与本文标签相同的文章
上一篇 :
Lazada双十一大促决定执行的系统降级通知
下一篇 :
华科云商:拨号VPS只是我们成功的第一步
-
GSMA首席执行官洪曜庄:5G时代中国在引领
2026-05-14栏目: 教程
-
猎户星空CEO傅盛:现在是AI发展最好时期,家庭服务机器人前景可期
2026-05-14栏目: 教程
-
5G远程驾驶和微公交首秀互联网大会
2026-05-14栏目: 教程
-
学宏程序编程,这些知识必不可少!
2026-05-14栏目: 教程
-
华为准备卖出“落后”的5G,多家美企极力竞争!任正非格局太大!
2026-05-14栏目: 教程
